Elect Design and Analy Engr 5

Our client is currently seeking a Elect Design and Analy Engr 5 which need active secret clearance

Job Code: Elect Design and Analy Engr 5

Work Location: El Segundo, CA

Shifts: 1st shift: 8:00 AM - 4:30 PM

NEED ACTIVE SECRET CLEARANCE TO START WITH

Job Description:

The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores.

- Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity.

- The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families.

- Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system.

- Therefore, on-site work is required.

Required Skills:

• 5+ years of FPGA and/or ASIC design experience.

• strong Xilinx/AMD Vivado experience.

• Experience with Versal family devices.

• Verilog/SystemVerilog HDL proficiency required.

• Advanced FPGA implementation skills (synthesis, timing closure, constraints);

• Active U.S. security clearance

Preferred Skills:

• 2+ years of FPGA design experience.

• strong Xilinx/AMD Vivado experience.

• Verilog/SystemVerilog proficiency.

• Advanced FPGA implementation skills (synthesis, timing closure, constraints);