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RF/Microelectronics Packaging Engineer

Mount Indie, LLC

Posted today

Job Requirements

Tempe, AZ
DoE Q or L Polygraph Unspecified
Career Level not specified
Salary not specified
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Job Description

We are seeking a Packaging Engineer to lead end-to-end packaging development for advanced microelectronic and RF communication products. This role is responsible for planning, designing, and delivering innovative packaging solutions across a range of technologies, including integrated circuits (ICs), system-in-package (SiP), sub-assemblies, and modules.

You will own the full packaging lifecycle-from concept and definition through design, modeling, testing, and production release-while partnering closely with cross-functional engineering teams and external vendors. This position requires deep technical expertise in semiconductor packaging, strong problem-solving skills, and the ability to drive development in a fast-paced, high-reliability environment.

Responsibilities
  • Collaborate with product development teams (RFIC, MMIC, and module engineering) to design and deliver next-generation packaging solutions for RF communication systems
  • Define package architectures, materials, and processes that meet performance, reliability, manufacturability, and cost requirements
  • Lead packaging efforts for new product introductions (NPI) and new technology development
  • Develop and manage packaging documentation, including statements of work (SOWs), drawings, and process flows
  • Design and layout semiconductor packages such as QFN, SiP, WL-CSP, RDL, Flip Chip, FO-WLP, and interposers
  • Utilize modeling and simulation (thermal, mechanical, electrical) to ensure early-stage design success
  • Provide technical oversight to external vendors and manufacturing partners throughout package fabrication
  • Apply expertise in assembly processes (die attach, wirebond, bumping, overmolding) to guide design decisions and troubleshoot issues
  • Evaluate and recommend packaging solutions through feasibility studies for new products
  • Partner with engineering teams to optimize packaging for cost and performance
  • Define and oversee reliability testing to ensure product robustness and compliance
  • Coordinate cross-functional efforts across design, test, quality, manufacturing, and supply chain teams
  • Identify and resolve material and process challenges during development
  • Manage packaging projects using industry-standard tools and methodologies
  • Contribute to long-term packaging technology roadmaps and support proposal efforts


Qualifications
  • 10+ years of experience in semiconductor packaging, including package engineering, assembly processes, and reliability
  • Bachelor's degree in Electrical, Mechanical, Materials Engineering, or a related technical field
  • Strong understanding of microelectronic packaging, including mechanical, electrical, and thermal performance considerations
  • Solid foundation in heat transfer and material properties
  • Experience supporting RFIC, millimeter wave, SiP, or module-based products
  • Hands-on experience with package design technologies such as QFN, SiP, BGA, WL-CSP, Flip Chip, bumping, or FO-WLP
  • Knowledge of semiconductor assembly processes, including die prep, die attach, wirebonding, flip chip, and SMT
  • Familiarity with interconnect reliability testing (e.g., daisy chain, CPI, BLR)
  • Understanding of metallization schemes for laminates, interposers, and SMT
  • Experience with statistical analysis and design of experiments (DOE)
  • Ability to operate independently and drive technical decisions in ambiguous environments
  • Strong communication and collaboration skills across cross-functional teams
  • Experience translating system or IC requirements into packaging solutions


Additional Requirements
  • U.S. Citizenship required
  • Ability to travel up to 10%
group id: 91082210