Design/Hardware Verification Engineer

As a Design Verification Engineer, you will work closely with our RTL development engineers, system architects, and software engineers to verify functional correctness and robustness of the RTL powering our next generation, FPGA-based secure communications systems. You will be responsible for RTL verification at both the unit and system level, as well as creating and maintaining the verification environment and test cases. A key aspect of this job is closely collaborating across both small and large project teams to understand the functional and performance goals of the system, use cases and edge cases, and use that knowledge to develop effective test plans and test cases. Experience in RTL design and development and FPGA implementation is a plus, and the ideal candidate will have the opportunity to work on both verification and design/implementation tasks.
Responsibilities: What is the day-to-day routine for this candidate? ·
• Own the verification of custom RTL blocks, subsystems, and full FPGA-level functionality ·
• Work with RTL design engineers and system architects to define verification plans based on system specifications, design goals, and use cases ·
• Develop and maintain verification environment in SystemVerilog/UVM including constrained-random, directed, and system-level testbenches ·
• Develop and maintain stimulus generators, drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces ·
• Work closely with RTL design engineers to triage and resolve bugs, owning and driving technical issues to resolution ·
• Collect and report code and functional coverage ·
• Maintain regular simulation regressions.
Qualifications:
• Bachelor’s degree in electrical engineering, Computer Engineering, or a related field
• 5+ years’ experience in hardware verification using SystemVerilog/UVM ·
• Proven success verifying complex RTL designs in industry-standard flows, including creation and maintenance of verification environment, test benches, and test cases.
• Proficient in SystemVerilog, UVM, and common simulation and debug tools including Siemens Questa ·
• Experience with Object Oriented Programming ·
• Experience with industry standard EDA tools (Cadence, Synopsys, and/or Mentor) ·
• Foundational knowledge of digital logic and timing considerations ·
• Strong written and verbal communication skills, ability to work with a geographically distributed team ·
• Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback ·
• Desire to be a member of a team, collaborating on large system designs ·
• Work independently, take initiative, and take ownership of tasks and results ·
• US citizenship required ·
• Active United States Secret Security Clearance ·
• Ability to travel up to 10%
• This is a 100% on-site role working from our office in one of these locations: Carlsbad, CA, or Marlborough, MA