Posted today
Top Secret/SCI
Senior Level Career (10+ yrs experience)
$282,000 - $315,840
None
IT - Hardware
Arlington, VA (On-Site/Office)
Candidates must already possess an active Top Secret/SCI to be considered for this position.
Apply in 60 seconds at https://apply.systolic.com
Summary:
Develop and implement FPGA verification strategies, including formal methods and UVM-based environments. Create and execute formal verification test plans, implement formal property verification and equivalence checking, and develop coverage-driven verification methodologies. Build automated test frameworks and apply formal methods for security-critical design blocks.
Qualifications & Compensation:
The ideal candidate will develop and implement comprehensive verification strategies, including formal methods, for complex FPGA designs in high-assurance applications. You will develop UVM-based verification environments, create and execute formal verification test plans, implement formal property verification and equivalence checking, and develop coverage-driven verification methodologies.
Key responsibilities include creating automated test frameworks, applying formal methods for security-critical design blocks, and collaborating with RTL developers to ensure design quality.
Annual compensation: $282,000-$315,840, based on experience level
About SYSTOLIC:
SYSTOLIC is dedicated to giving our employees the best possible company experience so that they can focus on providing outstanding support to their customer’s mission. Our company is founded on integrity, enthusiasm, and a relentless commitment to supporting the Intelligence Community. You can learn more about us and submit an application to be considered against our current and future openings at https://systolic.com.
To learn about our compensation ranges, visit our Pay Transparency page at: https://systolic.com/pay-transparency
Apply in 60 seconds at https://apply.systolic.com
Summary:
Develop and implement FPGA verification strategies, including formal methods and UVM-based environments. Create and execute formal verification test plans, implement formal property verification and equivalence checking, and develop coverage-driven verification methodologies. Build automated test frameworks and apply formal methods for security-critical design blocks.
Qualifications & Compensation:
The ideal candidate will develop and implement comprehensive verification strategies, including formal methods, for complex FPGA designs in high-assurance applications. You will develop UVM-based verification environments, create and execute formal verification test plans, implement formal property verification and equivalence checking, and develop coverage-driven verification methodologies.
Key responsibilities include creating automated test frameworks, applying formal methods for security-critical design blocks, and collaborating with RTL developers to ensure design quality.
Annual compensation: $282,000-$315,840, based on experience level
About SYSTOLIC:
SYSTOLIC is dedicated to giving our employees the best possible company experience so that they can focus on providing outstanding support to their customer’s mission. Our company is founded on integrity, enthusiasm, and a relentless commitment to supporting the Intelligence Community. You can learn more about us and submit an application to be considered against our current and future openings at https://systolic.com.
To learn about our compensation ranges, visit our Pay Transparency page at: https://systolic.com/pay-transparency
group id: 10527119
