Yesterday
Top Secret/SCI
Mid Level Career (5+ yrs experience)
Unspecified
Engineering - Electrical
Camden, NJ (On-Site/Office)
OUR PROJECT
Immediate opportunity to join our team and developing cutting-edge communications systems.
This is a long-term contract position that will be on a 9/80 schedule onsite at our Camden, NJ facility. Active Secret Clearance is required for this role. You can expect very competitive pay.
WHO WE ARE LOOKING FOR
We are looking for a Senior Electrical Systems Design Engineer to join our team working to deliver a cutting-edge communications system and with robust testing. You will be responsible for developing on Xilinx FPGAs with the Vivado Design Suite, and the testing and execution of RTL, HLS and quality checks. Experience working with TCP/IP, UDP/IP, and Ethernet protocols is required. Proficiency with VHDL and is required. Hands-on experience with Mentor EDA (Siemens EDA) is desired. 10+ years of progressive development experience is desired as demonstrated experience driving software driven validation is required. This is a fantastic opportunity to join a team delivering new technologies.
We are interviewing qualified candidates immediately and will move into the offer stage quickly. If you are interested, please apply with an updated resume.
QUALIFICATIONS
• 10+ years of Electrical Design Experience with Xilinx and Vivado Design Suite
• Proficiency with VHDL and C/C++ to execute design and quality for RTL and HLS
• Experience with Mentor EDA (Siemens EDA) and Synopsis Design Controller
• Experience with TCP/IP, UDP/IP, and Ethernet protocols
• Experience with 10gb Ethernet protocols is a plus
Immediate opportunity to join our team and developing cutting-edge communications systems.
This is a long-term contract position that will be on a 9/80 schedule onsite at our Camden, NJ facility. Active Secret Clearance is required for this role. You can expect very competitive pay.
WHO WE ARE LOOKING FOR
We are looking for a Senior Electrical Systems Design Engineer to join our team working to deliver a cutting-edge communications system and with robust testing. You will be responsible for developing on Xilinx FPGAs with the Vivado Design Suite, and the testing and execution of RTL, HLS and quality checks. Experience working with TCP/IP, UDP/IP, and Ethernet protocols is required. Proficiency with VHDL and is required. Hands-on experience with Mentor EDA (Siemens EDA) is desired. 10+ years of progressive development experience is desired as demonstrated experience driving software driven validation is required. This is a fantastic opportunity to join a team delivering new technologies.
We are interviewing qualified candidates immediately and will move into the offer stage quickly. If you are interested, please apply with an updated resume.
QUALIFICATIONS
• 10+ years of Electrical Design Experience with Xilinx and Vivado Design Suite
• Proficiency with VHDL and C/C++ to execute design and quality for RTL and HLS
• Experience with Mentor EDA (Siemens EDA) and Synopsis Design Controller
• Experience with TCP/IP, UDP/IP, and Ethernet protocols
• Experience with 10gb Ethernet protocols is a plus
group id: 10507524
