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Process Integration Engineer - Superconducting Technologies

HRL Laboratories

Today
DoE Q or L
Unspecified
Unspecified
Malibu, CA (On-Site/Office)

General Description:

The Interconnect and Integrated Devices Group at HRL Laboratories is a highly talented team of scientists and engineers with diverse backgrounds in integrated circuit design, microfabrication, advanced packaging and integration, materials characterization, and device test. This team is focused on rapidly developing new technologies and transitioning them out of the research lab and into the development pipeline.

We seek a process integration engineer with superconducting device experience to support new technology development. The ideal candidate is collaborative and has hands-on experience with superconducting device design, fabrication, and test. In this role you will support prototyping, process development, and packaging activities.

Essential Duties:

As an integration engineer in the Interconnect and Integrated Devices Group, you will act as a program interface to manage process development in our internal foundry and support process transfer to external vendors. Responsibilities will include:

Develop processes and integration schemes to support superconducting device architectures

Document processes, prepare reports, review inline metrology and electrical data, and perform failure and root cause analyses.

Support mask design and tape-out activities by defining design rules and participating in final mask data reviews to ensure process compliance

Support technical activities at subcontractors and vendors

Required Skills:

This role requires a collaborative and progress-oriented engineer who possesses the following skills:

Cleanroom fabrication experience

Semiconductor process development

Semiconductor device physics

Demonstrated ability to solve complex technical problems.

Ability to clearly communicate technical topics to a range of audiences.

Expertise with Statistical Process Contol (SPC) is desired

Data analysis and DOE using JMP or similar software is desired

Experience with packaging and/or 3D integration is desired

Experience with superconductor device design, fabrication, and test is desired

Data analysis using JMP or similar statistical analysis tools is desired

Required Education:

M.S. degree in Electrical Engineering, Physics, Chemistry, Materials Science, or a STEM related field plus 2+ years of relevant experience in semiconductor wafer processing

Advanced degree preferred

Physical Requirements:

Must be willing to work in a cleanroom (up to 30%)

Special Requirements:

U.S. citizenship is required.

Must be able to obtain and maintain a security clearance

Active SSBI strongly preferred

Compensation:

The base salary range for this full-time position is $132,765 - $165,983 + bonus + benefits.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range during the hiring process. Please note that the compensation details listed reflect the base salary only, and do not include potential bonus or benefits.
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Clearance Level
DoE Q or L