Lead ASIC Verification Engineer

Lead ASIC Verification Engineer

Location: Boise, ID

Pay Rate: $90 - $114/hr

Active Department of Defense Secret Security Clearance required at time of hire.

U.S. Citizenship required.

Additional Locations:

Salt Lake City, UT - Scottsdale, AZ - San Jose, CA

We are hiring a Lead ASIC Verification Engineer to support advanced defense electronics and embedded hardware security development. This position is based in Boise, ID , with additional locations in Salt Lake City, UT; Scottsdale, AZ; and San Jose, CA. Candidates must possess an active DoD Secret security clearance and extensive experience with ASIC/SoC verification, SystemVerilog, Universal Verification Methodology (UVM), RTL verification, simulation, functional coverage, and automated regression testing .

The Lead ASIC Verification Engineer will support the Bittercloud II program , leading block-level, subsystem-level, and full-chip verification for secure processors, anti-tamper architectures, cryptographic intellectual property (IP), and integrated hardware security technologies. This role combines hands-on verification engineering, technical leadership, requirements traceability, and cross-functional collaboration to support government cybersecurity, hardware security, and survivability requirements.

Repsonsibilities

• Lead ASIC and System-on-Chip (SoC) verification activities at the block, subsystem, and full-chip levels.
• Develop verification strategies, test plans, schedules, coverage goals, and completion criteria.
• Design, develop, and maintain reusable SystemVerilog/UVM testbenches, verification environments, and test components.
• Define ASIC/FPGA test and simulation plans, module interfaces, and verification requirements in coordination with design and architecture teams.
• Translate system and hardware requirements into measurable verification objectives, test cases, and coverage metrics.
• Maintain requirements traceability through test execution, verification results, defect resolution, and closure.
• Plan and execute simulation, automated regression testing, formal verification, and hardware emulation activities.
• Analyze coverage metrics, regression results, and verification progress against established completion goals.
• Investigate simulation failures, perform root-cause analysis, and verify corrective actions.
• Verify custom and third-party IP for functional correctness, interface compatibility, and system integration.
• Collaborate with RTL design, hardware architecture, firmware, and engineering teams to resolve design and verification issues.
• Identify verification risks, develop mitigation strategies, and communicate technical impacts to program stakeholders.
• Prepare and present verification status, technical evidence, risks, and recommendations during engineering reviews.
• Develop and maintain verification plans, test procedures, engineering documentation, and technical reports.
• Improve verification automation, reusable test environments, engineering metrics, and organizational processes.
• Provide technical leadership, direction, and mentoring to ASIC verification engineers.
• Support vendor oversight, technical proposals, engineering estimates, and program planning as required.
• Use approved AI-enabled engineering tools when appropriate while protecting sensitive program information.

Qualifications

• U.S. Citizenship required.
• Active DoD Secret Security Clearance required at time of hire.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related Science, Engineering, or Mathematics discipline plus a minimum of 10 years of relevant experience; OR Master's degree in a related discipline plus a minimum of 8 years of relevant experience.
• Strong knowledge of ASIC and SoC verification processes, methodologies, and workflows.
• Advanced proficiency in SystemVerilog, UVM, assertions, functional coverage, and regression testing.
• Experience developing reusable verification testbenches, test components, and register models.
• Strong understanding of RTL, digital logic, hardware interfaces, clocking, and reset architectures.
• Ability to translate technical requirements into measurable verification objectives, test cases, and completion criteria.
• Experience debugging ASIC simulations, investigating failures, and determining root causes.
• Experience with scripting languages such as Perl, Tcl, Bash, and Python.
• Experience using ASIC simulation and debugging tools such as VCS, Verdi, Questa, or equivalent tools.
• Experience with Linux, version control systems, and automated regression environments.
• Ability to communicate technical findings, verification results, and engineering risks to technical teams and stakeholders.
• Ability to lead multiple engineering activities while maintaining quality and schedule requirements.
• Demonstrated technical judgment, mentoring capabilities, and engineering problem-solving skills.

Preferred Qualifications

• Experience with formal verification, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), or low-power verification.
• Experience with hardware emulation, silicon bring-up, or post-silicon validation.
• Experience verifying third-party IP and complex digital interfaces.
• Experience working in Agile development environments.
• Experience supporting vendor oversight, engineering proposals, estimates, or program controls.