Job Requirements
Rolling Meadows, IL
Secret Polygraph Unspecified
Career Level not specified
Salary not specified
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Job Description
PDS Defense, Inc. is seeking a Digital Engineer 3, in Rolling Meadows, IL. Job ID#226992
Pay Rate: $94 - $99/hr
Job Description:
Designs, develops, modifies and evaluates digital electronic parts, components or integrated circuitry for digital electronic equipment and other hardware systems. Determines design approaches and parameters. Analyzes equipment to establish operating data, conducts experimental tests, and evaluates results. Selects components and equipment based on analysis of specifications and reliability. May also review vendor capability to support product development.
The Digital Design Engineer role involves full life-cycle product development from system concept and requirements through design, implementation, test verification, production, and field support. Digital subsystem and circuit card designs utilize the latest FPGA technologies from all major vendors and device families including Xilinx and Intel (Altera), and support high speed interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing, and processor interfaces. Your expertise in digital design and analysis, coding, verification, and synthesis using state of the art tools and techniques are desired for this position.
Basic Qualifications for Engineer Digital 3
Bachelor's degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 9 years of digital electronics design experience or 7 years of digital electronics design experience with a master's degree in a technical field.
Extensive digital hardware circuit design experience, including simulation and schematic capture through test and integration.
Ability to translate system performance and operational requirements into embedded system requirements, design, and test specifications
Experience in HDL (VHDL/Verilog)
A thorough understanding of synthesis static timing closure, physical build (implementation) and image generation. Strong testbench generations and verification. Experience using Xilinx Vivado, Synopsys Synplify Pro and Mentor Graphics QuestaSim.
Implementation of real time Digital Signal Processing algorithms within FPGAs. Experience with high-speed digital design techniques such as pipelining, asynchronous clock domains, synchronization, finite state machines, multi-cycling, and use of FIFOs.
Familiarity with documentation and revision control
Proven skills to include team leadership, mentoring others, communicating with all levels of an organization internally and externally, being adaptable, creative, collaborative, comfortable working independently, and enjoys solving difficult problems.
Current Secret Security Clearance.
Preferred Qualifications for Engineer Digital 3
Advanced degree in Electrical or Computer Engineering with a minimum 12 years of digital electronics design xperience.
Algorithm modeling using Matlab to generate bit-exact test vectors is desiredWorking knowledge of Electronic Warfare systems.
Experience in Aerospace and/or Defense industries.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
Pay Rate: $94 - $99/hr
Job Description:
Designs, develops, modifies and evaluates digital electronic parts, components or integrated circuitry for digital electronic equipment and other hardware systems. Determines design approaches and parameters. Analyzes equipment to establish operating data, conducts experimental tests, and evaluates results. Selects components and equipment based on analysis of specifications and reliability. May also review vendor capability to support product development.
The Digital Design Engineer role involves full life-cycle product development from system concept and requirements through design, implementation, test verification, production, and field support. Digital subsystem and circuit card designs utilize the latest FPGA technologies from all major vendors and device families including Xilinx and Intel (Altera), and support high speed interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing, and processor interfaces. Your expertise in digital design and analysis, coding, verification, and synthesis using state of the art tools and techniques are desired for this position.
Basic Qualifications for Engineer Digital 3
Bachelor's degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 9 years of digital electronics design experience or 7 years of digital electronics design experience with a master's degree in a technical field.
Extensive digital hardware circuit design experience, including simulation and schematic capture through test and integration.
Ability to translate system performance and operational requirements into embedded system requirements, design, and test specifications
Experience in HDL (VHDL/Verilog)
A thorough understanding of synthesis static timing closure, physical build (implementation) and image generation. Strong testbench generations and verification. Experience using Xilinx Vivado, Synopsys Synplify Pro and Mentor Graphics QuestaSim.
Implementation of real time Digital Signal Processing algorithms within FPGAs. Experience with high-speed digital design techniques such as pipelining, asynchronous clock domains, synchronization, finite state machines, multi-cycling, and use of FIFOs.
Familiarity with documentation and revision control
Proven skills to include team leadership, mentoring others, communicating with all levels of an organization internally and externally, being adaptable, creative, collaborative, comfortable working independently, and enjoys solving difficult problems.
Current Secret Security Clearance.
Preferred Qualifications for Engineer Digital 3
Advanced degree in Electrical or Computer Engineering with a minimum 12 years of digital electronics design xperience.
Algorithm modeling using Matlab to generate bit-exact test vectors is desiredWorking knowledge of Electronic Warfare systems.
Experience in Aerospace and/or Defense industries.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
- The California Fair Chance Act
- Los Angeles City Fair Chance Ordinance
- Los Angeles County Fair Chance Ordinance for Employers
- San Francisco Fair Chance Ordinance
group id: 9117PDSD