Job Requirements
Mountain View, CA
Secret Polygraph Unspecified
Career Level not specified
Salary not specified
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Job Description
PDS Defense, Inc. is seeking an Elect Design and Analy Engr 4, in Mountain View, CA.
Pay Rate: $80 - $85/hr
Job Description:
* Write SystemVerilog/UVM testbenches to verify ASICs and FPGAs.
* Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
* Build functional coverage models and close code coverage gaps.
* Create tests that verify DSP and third-party IP integration.
* Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.
* Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.
* Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.
* Collaborate with system and hardware teams to capture requirements and debug issues.
Required Skills
* Bachelor's degree in EE, CE, CS, or related field (or equivalent experience).
* Experience with ASIC/FPGA verification using SystemVerilog and UVM.
* Ability to build self-checking testbenches and use object-oriented SV features.
* Familiarity with functional coverage and code coverage closure.
* Comfortable in Linux and using scripting tools.
Preferred Skills
* 2+ years (Associate) or 5+ years (Experienced) verification experience.
* Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
* Knowledge of high-speed SerDes (PCIe, Ethernet, JESD204C).
* Experience with SVA (SystemVerilog Assertions) and RTL-to-GDS flows.
* Familiar with space/radiation mitigation techniques is a plus.
Education / Experience: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience (e.g. PhD+4 years' related work experience, Master+7 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
Pay Rate: $80 - $85/hr
Job Description:
* Write SystemVerilog/UVM testbenches to verify ASICs and FPGAs.
* Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
* Build functional coverage models and close code coverage gaps.
* Create tests that verify DSP and third-party IP integration.
* Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.
* Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.
* Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.
* Collaborate with system and hardware teams to capture requirements and debug issues.
Required Skills
* Bachelor's degree in EE, CE, CS, or related field (or equivalent experience).
* Experience with ASIC/FPGA verification using SystemVerilog and UVM.
* Ability to build self-checking testbenches and use object-oriented SV features.
* Familiarity with functional coverage and code coverage closure.
* Comfortable in Linux and using scripting tools.
Preferred Skills
* 2+ years (Associate) or 5+ years (Experienced) verification experience.
* Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
* Knowledge of high-speed SerDes (PCIe, Ethernet, JESD204C).
* Experience with SVA (SystemVerilog Assertions) and RTL-to-GDS flows.
* Familiar with space/radiation mitigation techniques is a plus.
Education / Experience: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience (e.g. PhD+4 years' related work experience, Master+7 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
- The California Fair Chance Act
- Los Angeles City Fair Chance Ordinance
- Los Angeles County Fair Chance Ordinance for Employers
- San Francisco Fair Chance Ordinance
group id: 9117PDSD