Circuit Design Engineer

Circuit Design Engineer


Clearance Level: Must have an Active Secret Clearance to be considered for this opportunity due to the nature of the work. Must be US Citizen 


Location: This role is 100% remote – must be willing to travel up to 3 times a year.


At Aquila Technology, you will see our team’s passion every day, whether we are building a robust, policy-compliant IT system or stress-testing a system to identify gaps and security vulnerabilities. To own the advantage, we ensure our team owns results and gets the work done right the first time by deploying smart, purposeful solutions that work. Aquila is the right people with the right skills driving the right outcomes. We call this the Aquila Advantage.


About the Role:


Aquila Technology is seeking a Circuit Design Engineer to support one of the nation’s premier defense research organizations. The team develops custom digital & mixed-signal Readout Integrated Circuits (ROICs) for advanced imager applications. An analog/mixed-signal layout design engineer is needed for implementation of imager circuit building blocks.


Must Have

• Clearance Level: Currently holds a Secret Clearance (OR a higher clearance)


• 10 years – Cadence IC design flow with layout, DRC, LVS, and parasitic extraction using Calibre and Assura


• 10 years – Eexperience in top level floor planning as well as block level design


• 10 years – Experience with multiple design tape outs


• 10 years – Deep-submicron CMOS Layout (12nm – 22nm, Global Foundries)


• Presentation, verbal and written communication skills


• Strong team communication


• Strong Verbal and Written Communication
  

Responsibilities include but are not limited to:

• Physical layout and verification of integrated circuit building blocks


• Full-chip assembly and top-level verification.


• Use best-practices for managing local process variation through layout techniques as well as high-speed digital and RF layout techniques to minimize unwanted parasitic interactions.

Must Have:

• Experience in deep-submicron CMOS layout across technologies including 12-65 nm design nodes in multiple foundries such as Global Foundries, onsemi and Tower Jazz


• Cadence integrated circuit design flow including layout, DRC, LVS and parasitic extraction through the use of Calibre and Assura.


• Proven track record of multiple design tape outs


• Extensive experience in top level floor planning as well as block level design


• Strong interpersonal and organizational skills along with strong written/verbal skills are required to support a multi-person design team in an effective way.

Work Location: Work from Home: This position is REMOTE. The candidate is able to work remotely from any location. They may be asked to take up to 3+ trips per calendar year to Lexington if the program/project requires it.


Core Work Hours: This position is a part time role with up to 24hrs a week.


Clearance Level: An ACTIVE clearance is required for this role. Do not submit candidates who do not meet this requirement.


Interview Process: 1st round will be a Zoom with the hiring manager. 2nd round will be a Zoom with additional team members as needed.


We are an Equal Opportunity Employer