Job Requirements
El Segundo, CA
Secret Polygraph Unspecified
Career Level not specified
Salary not specified
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Job Description
PDS Defense, Inc. is seeking an Elect Design and Analy Engr 5, in El Segundo, CA. Job ID#224980
Pay Rate: $95.00 - $119.00
Job Description:
Regular and predictable attendance is required
Work statement is a non-managerial role, non-leadership role.
The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultra scale, and Ultra scale+ families.
Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system. Therefore, on-site work is required.
Required Skills:
* 5+ years of FPGA and/or ASIC design experience;
* Strong Xilinx/AMD Vivado experience;
* Experience with Versal family devices;
* Verilog/System Verilog HDL proficiency required;
* Advanced FPGA implementation skills (synthesis, timing closure, constraints);
* Active U.S. security clearance
Preferred Skills:
* 2+ years of FPGA design experience;
* Strong Xilinx/AMD Vivado experience;
* Verilog/System Verilog proficiency;
* Advanced FPGA implementation skills (synthesis, timing closure, constraints);
General Recruiting Guidance
Across all positions, we are looking for engineers who:
* Demonstrate strong digital hardware fundamentals.
* Exercise sound engineering judgment.
* Work independently with minimal oversight.
* Communicate clearly and proactively.
* Produce high-quality technical documentation.
* Take ownership of their work and deliver maintainable engineering solutions.
* Recruiters should prioritize candidates who can clearly explain their personal technical contributions, design decisions, debugging approach, and ownership of deliverables, rather than simply listing tools or technologies used on a project.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
Pay Rate: $95.00 - $119.00
Job Description:
Regular and predictable attendance is required
Work statement is a non-managerial role, non-leadership role.
The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultra scale, and Ultra scale+ families.
Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system. Therefore, on-site work is required.
Required Skills:
* 5+ years of FPGA and/or ASIC design experience;
* Strong Xilinx/AMD Vivado experience;
* Experience with Versal family devices;
* Verilog/System Verilog HDL proficiency required;
* Advanced FPGA implementation skills (synthesis, timing closure, constraints);
* Active U.S. security clearance
Preferred Skills:
* 2+ years of FPGA design experience;
* Strong Xilinx/AMD Vivado experience;
* Verilog/System Verilog proficiency;
* Advanced FPGA implementation skills (synthesis, timing closure, constraints);
General Recruiting Guidance
Across all positions, we are looking for engineers who:
* Demonstrate strong digital hardware fundamentals.
* Exercise sound engineering judgment.
* Work independently with minimal oversight.
* Communicate clearly and proactively.
* Produce high-quality technical documentation.
* Take ownership of their work and deliver maintainable engineering solutions.
* Recruiters should prioritize candidates who can clearly explain their personal technical contributions, design decisions, debugging approach, and ownership of deliverables, rather than simply listing tools or technologies used on a project.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
- The California Fair Chance Act
- Los Angeles City Fair Chance Ordinance
- Los Angeles County Fair Chance Ordinance for Employers
- San Francisco Fair Chance Ordinance
group id: 9117PDSD