FPGA and DSP Engineers

Below are some details of the positions we are hiring for. Keep in mind you do not need all credentials below.

Team Structure & Mix
- 2–3 FPGA Design Engineers per 1 Verification Engineer
- Approx. 8–10 engineers needed in El Segundo and Fullerton
- 2 -3 may be placed in Cedar Rapid

Design or verification backgrounds to contribute across requirements capture, digital architecture, RTL design, verification, and lab integration.
Design & Architecture:
- Requirements capture and development of FPGA/ASIC digital architectures
- RTL design and implementation in VHDL or Verilog
- Timing analysis and closure on high speed digital systems
- Resource trade off analysis and design optimization

Verification:
- Testbench development using VHDL or SystemVerilog / UVM
- Functional verification of RTL blocks and subsystems
- Support constrained-random, functional coverage, and best practice verification methodologies

Integration & Lab Work:
- Hands-on FPGA/ASIC validation using advanced lab equipment
- Work within secure, air gapped environments for system bring-up
- Integration support with multidisciplinary engineering teams

Required Qualifications
- Active Secret clearance at start
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
- Expertise in FPGA design and/or verification
- Strong VHDL experience
- Proficiency with Intel/Altera FPGA tools (preferred), Modelsim, Synopsys, and/or FPGA vendor toolchains
- Experience with high speed digital systems, interfaces, and signal processing
- Strong hands on lab experience (non negotiable)

Desired Skills
- SystemVerilog + UVM verification
- ASIC experience (nice-to-have)
- Design-for-Test (DFT) and manufacturability knowledge
- Unix/Linux, scripting, C/C++, or Perl experience