Job Requirements
Owego, NY
Secret Polygraph Unspecified
Career Level not specified
Salary not specified
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Job Description
PDS Defense, Inc. is seeking a Remote FPGA Design/Verification Engineer. Job ID#219240
Pay Rate: $80 - $100/hr
Job Description:
Review the architecture and translate high-level requirements into detailed FPGA designs.
Write Verilog code to implement the logic (e.g., data processing pipelines for ADP/DDP, serial comms for HSPCI).
Create Firmware Requirements Specifications (FRS) and Firmware Design Descriptions (FDD); these are formal deliverables tied to program milestones.
Simulate the designs to verify they behave correctly before hardware is ready.
Integration & Test
Load the FPGA code onto prototype hardware (ADP boards are already built; DDP/HSPCI are in development).
Support integration teams by fixing problems (PTRs) and refining the design as needed.
Required Skill:
Verilog
FPGA Design Toolchain (Vivado/Quartus)
RTL Coding & Simulation
Documentation (FRS/FDD)
Version Control (Git)
Review the architecture and translate high-level requirements into detailed FPGA designs.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
Pay Rate: $80 - $100/hr
Job Description:
Review the architecture and translate high-level requirements into detailed FPGA designs.
Write Verilog code to implement the logic (e.g., data processing pipelines for ADP/DDP, serial comms for HSPCI).
Create Firmware Requirements Specifications (FRS) and Firmware Design Descriptions (FDD); these are formal deliverables tied to program milestones.
Simulate the designs to verify they behave correctly before hardware is ready.
Integration & Test
Load the FPGA code onto prototype hardware (ADP boards are already built; DDP/HSPCI are in development).
Support integration teams by fixing problems (PTRs) and refining the design as needed.
Required Skill:
Verilog
FPGA Design Toolchain (Vivado/Quartus)
RTL Coding & Simulation
Documentation (FRS/FDD)
Version Control (Git)
Review the architecture and translate high-level requirements into detailed FPGA designs.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
- The California Fair Chance Act
- Los Angeles City Fair Chance Ordinance
- Los Angeles County Fair Chance Ordinance for Employers
- San Francisco Fair Chance Ordinance
group id: 9117PDSD