Job Requirements
El Segundo, CA
Secret Polygraph Unspecified
Career Level not specified
Salary not specified
Join Premium to unlock estimated salaries 
Job Description
PDS Defense, Inc. is seeking an Electrical Design and Analysis Engineer 5, in El Segundo, CA. Job ID#219051
Pay Rate: $99 - $104/hr
Job Description:
As an ASIC/FPGA Verification Engineer on the Electronic Products team you will develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise. We collaborate with other electronics groups across the company and around the world and support ASIC/FPGA design and verification for electronics that we build in El Segundo and for units designed at other sites.
Position Responsibilities:
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation.
Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time.
Assist in FPGA-based prototyping and validation based on program and system requirements and complexity.
Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines.
Required Skills:
A Bachelor of Science degree in Engineering (specializing in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or equivalent non-US qualifications relevant to the job description
Proven experience in ASIC/FPGA verification processes
Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM, including the delivery and release of production designs
Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions
Demonstrated experience in implementing test plans effectively
Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism
Capability to design self-checking and reusable testbenches from the ground up
Experience in developing Functional Coverage Models and achieving Code Coverage closure
Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications
Familiarity with waveform debug tools
Revision Control Systems: svn, cvs, git
Proficient in Linux Environments
Preferred Skills:
15+ years of related work experience or an equivalent combination of education and experience
Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience
Experience with hardware-based integration and test of ASIC/FPGA designs
Experience with hardware emulators, especially Palladium
Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
Proficient in scripting languages: Make, Perl, Python, etc.
Familiarity with space-based design techniques and radiation mitigation
Demonstrated history of 1st pass success with ASIC designs
Education / Experience:
A Bachelor of Science degree in Engineering (specializing in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
Pay Rate: $99 - $104/hr
Job Description:
As an ASIC/FPGA Verification Engineer on the Electronic Products team you will develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise. We collaborate with other electronics groups across the company and around the world and support ASIC/FPGA design and verification for electronics that we build in El Segundo and for units designed at other sites.
Position Responsibilities:
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation.
Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time.
Assist in FPGA-based prototyping and validation based on program and system requirements and complexity.
Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines.
Required Skills:
A Bachelor of Science degree in Engineering (specializing in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or equivalent non-US qualifications relevant to the job description
Proven experience in ASIC/FPGA verification processes
Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM, including the delivery and release of production designs
Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions
Demonstrated experience in implementing test plans effectively
Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism
Capability to design self-checking and reusable testbenches from the ground up
Experience in developing Functional Coverage Models and achieving Code Coverage closure
Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications
Familiarity with waveform debug tools
Revision Control Systems: svn, cvs, git
Proficient in Linux Environments
Preferred Skills:
15+ years of related work experience or an equivalent combination of education and experience
Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience
Experience with hardware-based integration and test of ASIC/FPGA designs
Experience with hardware emulators, especially Palladium
Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
Proficient in scripting languages: Make, Perl, Python, etc.
Familiarity with space-based design techniques and radiation mitigation
Demonstrated history of 1st pass success with ASIC designs
Education / Experience:
A Bachelor of Science degree in Engineering (specializing in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
- The California Fair Chance Act
- Los Angeles City Fair Chance Ordinance
- Los Angeles County Fair Chance Ordinance for Employers
- San Francisco Fair Chance Ordinance
group id: 9117PDSD