Job Requirements
Denver, CO Highlands Ranch, CO King of Prussia, PA Sunnyvale, CA Titusville, FL
Top Secret Polygraph not specified
Senior Level Career (10+ yrs experience)
$170,900 - $301,415
Job Description
The Global Edge Consultants, LLC is an Equal Opportunity Employer. The Global Edge Consultants, LLC does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.
Job Title: ASIC/FPGA Principal Verification Architect VI
Location: Denver, CO / Highlands Ranch, CO / King of Prussia, PA / Sunnyvale, CA / Titusville, FL
Type of Role: Direct Hire (Full-Time, Onsite)
Shift: 9x80 Schedule (Every other Friday off)
Pay: $$170,900-$301,415/year
POSITION OVERVIEW:
We are seeking an experienced ASIC/FPGA Principal Verification Architect VI to support advanced ASIC, FPGA, and SoC verification efforts within a highly integrated aerospace and defense environment. This role is responsible for driving verification and validation strategy across complex digital hardware programs while improving efficiency, scalability, and technical execution throughout the ASIC/FPGA development lifecycle. The ideal candidate has deep expertise in modern verification methodologies, strong technical leadership capabilities, and the ability to collaborate across hardware, software, and systems engineering teams supporting mission-critical avionics technologies.
RESPONSIBILITIES AND ESSENTIAL DUTIES:
• Serve as the Principal Subject Matter Expert (SME) for ASIC, FPGA, and SoC verification and validation efforts
• Develop roadmaps, processes, and scalable methodologies related to verification and validation of complex digital devices
• Architect advanced testing and simulation environments for complex custom and fixed SoC designs
• Develop and promote verification strategies that improve cost efficiency, scalability, and development timelines
• Mentor and train engineering teams on verification and validation best practices
• Continuously evaluate new verification tools, technologies, and methodologies while providing recommendations to leadership
• Collaborate closely with design, verification, and software teams to develop integrated engineering solutions
• Support all phases of ASIC/FPGA lifecycle activities including architecture, design, simulation, verification, validation, integration, and testing
• Develop business cases supporting verification and validation process improvements
• Lead technical reviews and present verification strategies and findings to internal and external stakeholders
MINIMUM REQUIREMENTS:
Basic Qualifications
• 12+ years of professional experience in FPGA and ASIC verification and validation
• Experience utilizing modern verification methodologies including UVM, Formal Verification, Emulation, lab validation, and related verification techniques
• Experience architecting advanced testing environments for complex ASIC, FPGA, and SoC systems
• Strong understanding of ASIC/FPGA lifecycle processes including architecture, design, simulation, verification, validation, integration, and test
• Experience leading cross-functional engineering teams including software and hardware developers
• Experience managing schedules, prioritizing work, and communicating effectively with internal and external stakeholders
• Ability to obtain and maintain a government-sponsored security clearance
• U.S. Citizenship required
Additional Qualifications
• Experience with formal verification methodologies including property checking, connectivity checking, FuSa, and coverage analysis
• Experience with hardware emulation platforms such as ZeBu or Palladium
• HDL programming experience with VHDL, Verilog, and/or SystemVerilog
• Experience developing FPGA/ASIC test benches and randomized stimulus environments
• Experience developing verification plans and test cases based on requirements
• Experience identifying and implementing verification exclusions and strategies
• Experience analyzing functional and code coverage results and generating coverage reports
• Experience mentoring and training engineers on verification methodologies and tools
• Experience presenting to executive leadership and customers
• Familiarity with older verification methodologies including OVM or VMM
• Familiarity with scripting languages such as Perl, TCL, and Python
• Experience with project management and collaboration tools such as MS Project and JIRA
• Knowledge of space-grade or space-qualified ASICs and FPGAs
• Experience driving process improvements and supporting program reviews
The Global Edge Consultants, LLC is an Equal Opportunity Employer. The Global Edge Consultants, LLC does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.
Job Title: ASIC/FPGA Principal Verification Architect VI
Location: Denver, CO / Highlands Ranch, CO / King of Prussia, PA / Sunnyvale, CA / Titusville, FL
Type of Role: Direct Hire (Full-Time, Onsite)
Shift: 9x80 Schedule (Every other Friday off)
Pay: $$170,900-$301,415/year
POSITION OVERVIEW:
We are seeking an experienced ASIC/FPGA Principal Verification Architect VI to support advanced ASIC, FPGA, and SoC verification efforts within a highly integrated aerospace and defense environment. This role is responsible for driving verification and validation strategy across complex digital hardware programs while improving efficiency, scalability, and technical execution throughout the ASIC/FPGA development lifecycle. The ideal candidate has deep expertise in modern verification methodologies, strong technical leadership capabilities, and the ability to collaborate across hardware, software, and systems engineering teams supporting mission-critical avionics technologies.
RESPONSIBILITIES AND ESSENTIAL DUTIES:
• Serve as the Principal Subject Matter Expert (SME) for ASIC, FPGA, and SoC verification and validation efforts
• Develop roadmaps, processes, and scalable methodologies related to verification and validation of complex digital devices
• Architect advanced testing and simulation environments for complex custom and fixed SoC designs
• Develop and promote verification strategies that improve cost efficiency, scalability, and development timelines
• Mentor and train engineering teams on verification and validation best practices
• Continuously evaluate new verification tools, technologies, and methodologies while providing recommendations to leadership
• Collaborate closely with design, verification, and software teams to develop integrated engineering solutions
• Support all phases of ASIC/FPGA lifecycle activities including architecture, design, simulation, verification, validation, integration, and testing
• Develop business cases supporting verification and validation process improvements
• Lead technical reviews and present verification strategies and findings to internal and external stakeholders
MINIMUM REQUIREMENTS:
Basic Qualifications
• 12+ years of professional experience in FPGA and ASIC verification and validation
• Experience utilizing modern verification methodologies including UVM, Formal Verification, Emulation, lab validation, and related verification techniques
• Experience architecting advanced testing environments for complex ASIC, FPGA, and SoC systems
• Strong understanding of ASIC/FPGA lifecycle processes including architecture, design, simulation, verification, validation, integration, and test
• Experience leading cross-functional engineering teams including software and hardware developers
• Experience managing schedules, prioritizing work, and communicating effectively with internal and external stakeholders
• Ability to obtain and maintain a government-sponsored security clearance
• U.S. Citizenship required
Additional Qualifications
• Experience with formal verification methodologies including property checking, connectivity checking, FuSa, and coverage analysis
• Experience with hardware emulation platforms such as ZeBu or Palladium
• HDL programming experience with VHDL, Verilog, and/or SystemVerilog
• Experience developing FPGA/ASIC test benches and randomized stimulus environments
• Experience developing verification plans and test cases based on requirements
• Experience identifying and implementing verification exclusions and strategies
• Experience analyzing functional and code coverage results and generating coverage reports
• Experience mentoring and training engineers on verification methodologies and tools
• Experience presenting to executive leadership and customers
• Familiarity with older verification methodologies including OVM or VMM
• Familiarity with scripting languages such as Perl, TCL, and Python
• Experience with project management and collaboration tools such as MS Project and JIRA
• Knowledge of space-grade or space-qualified ASICs and FPGAs
• Experience driving process improvements and supporting program reviews
The Global Edge Consultants, LLC is an Equal Opportunity Employer. The Global Edge Consultants, LLC does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.
group id: 91173864