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Engineer Digital 3

Artech Information Systems

Posted today

Job Requirements

San Diego, CA
Secret Polygraph Unspecified
Career Level not specified
Salary not specified
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Job Description

Job Title : Digital Engineer
Duration : 12 Months and Possible Extension
Location: San Diego, CA
TELECOMMUTE: No- Teleworking not available for this position
CLEARANCE TYPE: Active Secret Clearance
WORK SHIFT: 1st Shift (9/80A)
Pay Range : $90-$105/hr on W2 without benefits

Description :
We are looking for you to join our team as a Digital Engineer on site in San Diego, CA.

Responsibilities:

  • Design, develop, integrate and test VHDL-based digital designs for our end-user customers and businesses, primarily focused on software defined radio VHDL firmware code bases.
  • Work using FPGA programming development tools and environments
  • Work with multi-disciplinary teams, such as with Systems Engineering, Digital Engineering, Hardware, and Integration & Test
  • Work in waterfall or Agile software development environment
  • Analyze system concept of operation, requirements and design documents to resolve functional, performance or timing issues.


Must Have Qualifications for Digital Engineer:

  • BS + 5 years of experience in related STEM field; MS + 3 years of experience
  • Significant hands-on current experience in the field of VHDL design.
  • Candidate must have excellent written and communication skills and be able to work independently and within groups.
  • Candidate must have working knowledge of formal engineering development process, VHDL design and verification.
  • 8 or more years of professional technical experience.
  • Experience with VHDL design and OSVVM verification for FPGA firmware
  • Experience with AMD/Xilinx series including Zynq, Kintex, Ultrascale, Versal family of devices.
  • Experience with Communication Protocols (I2C, SPI, UART, PCIe, Ethernet)
  • Experience with Electronic Design Automation (EDA) tools: Vivado, Quartus, QuestaSim
  • Knowledgeable in FPGA physical constraints and achieving timing closure.
  • Generation of Test benches and support of formal VHDL Verification.
  • Experience with board RO system level debug using test equipment such as oscilloscopes and logic analyzers.
  • Experience with translating systems requirements into programmable logic requirements, design documents, and test specifications.
  • Candidate should have hands on experience with DoD communications systems.
group id: artech