Job Requirements
San Diego, CA
Secret Polygraph Unspecified
Career Level not specified
Salary not specified
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Job Description
Indotronix is seeking an :VHDL / Digital Engineer, San Diego California
Duration: 06 Months
Active Secret or interim is Must
WORK SHIFT: 1st Shift (9/80A)
BS + 5 years of experience
Responsibilities:
• Design, develop, integrate, and test VHDL-based digital designs, primarily for software-defined radio (SDR) firmware applications
• Develop and implement FPGA-based solutions using industry-standard programming tools and environments
• Collaborate with Systems Engineering, Digital Engineering, Hardware, and Integration & Test teams to deliver end-to-end solutions
• Work within Agile or waterfall development methodologies depending on project requirements
• Analyze system concepts of operation, requirements, and design documentation to identify and resolve functional, performance, and timing issues
• Perform design verification, validation, and debugging of FPGA firmware
• Support integration, system-level testing, and troubleshooting activities
Basic Qualifications:
• Bachelor's degree with 5+ years of experience in a related STEM field, or Master's degree with 3+ years of experience
• Strong hands-on experience in VHDL design and development
• Working knowledge of formal engineering development processes and VHDL verification methodologies
• Excellent written and verbal communication skills with the ability to work independently and in team environments
Preferred Qualifications:
• 8+ years of relevant technical experience in digital design and FPGA development
• Experience with VHDL design and OSVVM-based verification for FPGA firmware
• Hands-on experience with AMD/Xilinx FPGA families such as Zynq, Kintex, Ultrascale, and Versal
• Familiarity with communication protocols including I2C, SPI, UART, PCIe, and Ethernet
• Experience with Electronic Design Automation (EDA) tools such as Vivado, Quartus, and QuestaSim
• Strong understanding of FPGA timing constraints, physical implementation, and timing closure techniques
• Experience developing test benches and supporting formal VHDL verification
• Experience with board- or system-level debugging using oscilloscopes and logic analyzers
• Ability to translate system requirements into FPGA design specifications and test plans
• Experience working with DoD communication systems is a plus
Duration: 06 Months
Active Secret or interim is Must
WORK SHIFT: 1st Shift (9/80A)
BS + 5 years of experience
Responsibilities:
• Design, develop, integrate, and test VHDL-based digital designs, primarily for software-defined radio (SDR) firmware applications
• Develop and implement FPGA-based solutions using industry-standard programming tools and environments
• Collaborate with Systems Engineering, Digital Engineering, Hardware, and Integration & Test teams to deliver end-to-end solutions
• Work within Agile or waterfall development methodologies depending on project requirements
• Analyze system concepts of operation, requirements, and design documentation to identify and resolve functional, performance, and timing issues
• Perform design verification, validation, and debugging of FPGA firmware
• Support integration, system-level testing, and troubleshooting activities
Basic Qualifications:
• Bachelor's degree with 5+ years of experience in a related STEM field, or Master's degree with 3+ years of experience
• Strong hands-on experience in VHDL design and development
• Working knowledge of formal engineering development processes and VHDL verification methodologies
• Excellent written and verbal communication skills with the ability to work independently and in team environments
Preferred Qualifications:
• 8+ years of relevant technical experience in digital design and FPGA development
• Experience with VHDL design and OSVVM-based verification for FPGA firmware
• Hands-on experience with AMD/Xilinx FPGA families such as Zynq, Kintex, Ultrascale, and Versal
• Familiarity with communication protocols including I2C, SPI, UART, PCIe, and Ethernet
• Experience with Electronic Design Automation (EDA) tools such as Vivado, Quartus, and QuestaSim
• Strong understanding of FPGA timing constraints, physical implementation, and timing closure techniques
• Experience developing test benches and supporting formal VHDL verification
• Experience with board- or system-level debugging using oscilloscopes and logic analyzers
• Ability to translate system requirements into FPGA design specifications and test plans
• Experience working with DoD communication systems is a plus
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