Design Verification Engineer

This is a 100% on-site role working from the office in one of the following locations:

• Carlsbad, CA
• Marlborough, MA

You'll work with highly motivated engineers in an exciting and dynamic environment, using your engineering experience to help develop the next generation of advanced communications products and systems.

As a Design Verification Engineer, you will work closely with RTL development engineers, system architects, and software engineers to verify the functional correctness and robustness of RTL powering next-generation FPGA-based secure communications systems. You will be responsible for RTL verification at both the unit and system level, as well as creating and maintaining the verification environment and test cases.

A key aspect of this role is collaborating across both small and large project teams to understand system functionality, performance goals, use cases, and edge cases, and using that knowledge to develop effective verification plans and test cases. Experience in RTL design, development, and FPGA implementation is a plus, and the ideal candidate may have opportunities to work on both verification and design/implementation tasks.

Responsibilities

• Own verification of custom RTL blocks, subsystems, and full FPGA-level functionality
• Work with RTL design engineers and system architects to define verification plans based on system specifications, design goals, and use cases
• Develop and maintain verification environments in SystemVerilog/UVM, including constrained-random, directed, and system-level testbenches
• Develop and maintain stimulus generators, drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces
• Work closely with RTL design engineers to triage and resolve bugs, driving technical issues through resolution
• Collect and report code and functional coverage
• Maintain regular simulation regressions

Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field
• 5+ years of experience in hardware verification using SystemVerilog/UVM
• Proven success verifying complex RTL designs in industry-standard flows, including creation and maintenance of verification environments, testbenches, and test cases
• Proficient in SystemVerilog, UVM, and common simulation/debug tools (e.g., Siemens Questa)
• Experience with Object-Oriented Programming
• Experience with industry standard EDA tools (Cadence, Synopsys, and/or Mentor)
• Foundational knowledge of digital logic and timing considerations
• Strong written and verbal communication skills and ability to work with geographically distributed teams
• High attention to detail and ability to follow development processes and coding standards
• Ability to participate in code reviews and collaborate on large system designs
• Ability to work independently, take initiative, and take ownership of tasks and results
• US Citizenship required
• Active United States Secret Security Clearance required
• Ability to travel up to 10%