Posted today
Secret
Mid Level Career (5+ yrs experience)
Unspecified
Aerospace and Aviation
El Segundo, CA (On/Off-Site)
We are expanding our FPGA & ASIC Design Solutions team supporting next‑generation military GPS and high‑reliability digital systems. We are seeking experienced and motivated Senior Electrical or Computer Engineers with strong FPGA/ASIC design or verification backgrounds to contribute across requirements capture, digital architecture, RTL design, verification, and lab integration.
Key Responsibilities
Design & Architecture:
- Requirements capture and development of FPGA/ASIC digital architectures
- RTL design and implementation in VHDL or Verilog
- Timing analysis and closure on high‑speed digital systems
- Resource trade‑off analysis and design optimization
Verification:
- Testbench development using VHDL or SystemVerilog / UVM
- Functional verification of RTL blocks and subsystems
- Support constrained-random, functional coverage, and best‑practice verification methodologies
Integration & Lab Work:
- Hands-on FPGA/ASIC validation using advanced lab equipment
- Work within secure, air‑gapped environments for system bring-up
- Integration support with multidisciplinary engineering teams
Required Qualifications
- Active Secret clearance at start
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
- Expertise in FPGA design and/or verification
- Strong VHDL experience
- Proficiency with Intel/Altera FPGA tools (preferred), Modelsim, Synopsys, and/or FPGA vendor toolchains
- Experience with high‑speed digital systems, interfaces, and signal processing
- Ability to work independently and communicate clearly in documentation and presentations
- Strong hands‑on lab experience (non‑negotiable)
Desired Skills
- SystemVerilog + UVM verification
- ASIC experience (nice-to-have)
- Design-for-Test (DFT) and manufacturability knowledge
- Unix/Linux, scripting, C/C++, or Perl experience
Team Structure & Mix
- 2–3 FPGA Design Engineers per 1 Verification Engineer
- Approx. 8–10 engineers needed in El Segundo
- 1–2 may be placed in Cedar Rapids
Work Environment
- Air‑gapped, fully secure engineering lab
- Collins-issued badging and access
- Standard 40 hours/week; overtime possible with approval
- On-site only (no remote work)
Summary
This role is ideal for seasoned FPGA/ASIC engineers who excel in secure lab environments and want to contribute to mission‑critical military GPS and high‑speed digital systems.
Key Responsibilities
Design & Architecture:
- Requirements capture and development of FPGA/ASIC digital architectures
- RTL design and implementation in VHDL or Verilog
- Timing analysis and closure on high‑speed digital systems
- Resource trade‑off analysis and design optimization
Verification:
- Testbench development using VHDL or SystemVerilog / UVM
- Functional verification of RTL blocks and subsystems
- Support constrained-random, functional coverage, and best‑practice verification methodologies
Integration & Lab Work:
- Hands-on FPGA/ASIC validation using advanced lab equipment
- Work within secure, air‑gapped environments for system bring-up
- Integration support with multidisciplinary engineering teams
Required Qualifications
- Active Secret clearance at start
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
- Expertise in FPGA design and/or verification
- Strong VHDL experience
- Proficiency with Intel/Altera FPGA tools (preferred), Modelsim, Synopsys, and/or FPGA vendor toolchains
- Experience with high‑speed digital systems, interfaces, and signal processing
- Ability to work independently and communicate clearly in documentation and presentations
- Strong hands‑on lab experience (non‑negotiable)
Desired Skills
- SystemVerilog + UVM verification
- ASIC experience (nice-to-have)
- Design-for-Test (DFT) and manufacturability knowledge
- Unix/Linux, scripting, C/C++, or Perl experience
Team Structure & Mix
- 2–3 FPGA Design Engineers per 1 Verification Engineer
- Approx. 8–10 engineers needed in El Segundo
- 1–2 may be placed in Cedar Rapids
Work Environment
- Air‑gapped, fully secure engineering lab
- Collins-issued badging and access
- Standard 40 hours/week; overtime possible with approval
- On-site only (no remote work)
Summary
This role is ideal for seasoned FPGA/ASIC engineers who excel in secure lab environments and want to contribute to mission‑critical military GPS and high‑speed digital systems.
group id: indony
