Senior Power Integrity Engineer

Piper Companies is seeking a Senior Power Integrity Engineer to support a start up organization in the semiconductor and advanced hardware industry in San Jose, CA. The Senior Power Integrity Engineer will focus on the design, simulation, and verification of complex power delivery networks (PDNs) across chip, wafer, PCB, and advanced substrate-level systems. The Senior Power Integrity Engineer role requires you to sit onsite 5 days per week in San Jose, CA and is a direct placement with the company.

Responsibilities of the Senior Power Integrity Engineer:

• Architect, design, and refine power delivery networks (PDNs) for integrated circuits, wafers, printed circuit boards, and organic substrates.
• Develop detailed models and simulations of end-to-end power delivery paths, including pads, BGAs, routing layers, vias, and embedded capacitors.
• Perform static (DC) and dynamic (AC) power integrity analyses to assess system-level performance, noise margins, and power stability.
• Generate and interpret key PI deliverables such as impedance profiles, current-density maps, and power integrity validation reports.
• Recommend and drive improvements to ballmaps, stackups, routing guidelines, power planes, and decoupling strategies to achieve low-impedance, robust PDNs.
• Collaborate closely with silicon design, packaging, board design, and layout teams to ensure end-to-end power integrity across highly integrated hardware platforms.

Requirements of the Senior Power Integrity Engineer:

• 10+ years of experience in power integrity engineering or closely related roles.
• Hands-on experience using PI simulation and modeling tools such as ADS, MATLAB, Q3D, SiWave, or comparable industry tools.
• Deep understanding of vertical power delivery concepts and advanced PDN architectures for high-performance systems.
• Strong background in analog and digital circuit design principles and their impact on power delivery.
• Master's degree or higher in Electrical Engineering or a related technical field.

Compensation for the Senior Power Integrity Engineer:

• $200,000- $250,000 base salary
• Comprehensive Benefits: Medical, Dental, Vision, 401(k), PTO, Sick Leave as required by law, and Holidays

Keywords: senior power integrity engineer, power integrity, PDN design, power delivery networks, chip-level power delivery, wafer-level power integrity, PCB power integrity, organic substrate design, impedance analysis, DC drop analysis, AC noise analysis, current density modeling, ballmap optimization, stackup optimization, power plane design, decoupling strategy, PI modeling, PI simulation, ADS, MATLAB, Q3D, SiWave, analog circuit design, digital circuit design, vertical power delivery, advanced packaging, BGA power routing, San Jose CA, Secret clearance

This job opens for applications on 1/28/2026. Applications for this job will be accepted for at least 30 days from the posting date.

#LI-AG1

#LI-ONSITE