Senior Power Integrity Engineer

Piper Companies is seeking a Senior Power Integrity Engineer to support the design, simulation, and validation of power delivery networks (PDNs) for advanced chip, wafer, PCB, and substrate-level systems onsite in San Jose, CA . The ideal Senior Power Integrity Engineer has deep experience in power integrity analysis and enjoys solving complex power-delivery challenges across highly integrated hardware platforms.

Responsibilities for the Senior Power Integrity Engineer:

• Design, analyze, and validate power delivery networks (PDNs) for chips, wafers, PCBs, and organic substrates.
• Model and simulate power-delivery paths including pads, BGAs, routing layers, vias, and embedded capacitors.
• Perform DC and AC load analysis to evaluate system-level performance.
• Create impedance plots, current-density reports, and other key PI deliverables.
• Recommend improvements for ballmaps, routing rules, stackups, power planes, and decoupling strategies.
• Collaborate with design, packaging, and layout teams to ensure robust power-integrity performance.

Qualifications for the Senior Power Integrity Engineer:

• 10+ years of experience in Power Integrity engineering
• Must be eligible to work in the United States and obtain and maintain an Active U.S. Government Secret Clearance
• Hands-on experience with PI simulation tools such as ADS, MATLAB, Q3D, SiWave, or similar.
• Strong understanding of vertical power-delivery design and advanced PDN architectures.
• Solid background in analog and digital circuit design principles.
• Master's degree or higher in Electrical Engineering.

Compensation for the Senior Power Integrity Engineer:

• Salary Range : $200,000 - 250,000 annually based on experience
• Comprehensive Benefits: Medical, Dental, Vision, 401K, PTO, Sick Leave as required by law, and Holidays

This job opens for applications on 1/21/2026. Applications for this job will be accepted for at least 30 days from the posting date

Keywords: Power Integrity Engineer, PDN design, Power delivery networks, PDN analysis, chip-level power delivery, wafer-level power delivery, PCB power integrity, organic substrates, impedance analysis, DC/AC power analysis, ballmap optimization, stackup design, PI modeling, PI simulation, ADS, MATLAB, Q3D, SiWave, analog design, digital design, vertical power delivery, advanced packaging, BGA routing

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