Senior Standard Cell Design Engineer

⚙️ Shape the Future of Microelectronics at JRC!

Are you a visionary engineer driven by innovation and inspired by the challenge of pushing microelectronics to their limits? Join JRC's cutting-edge Radiation Hardened Semiconductor Technology Division as a Senior Standard Cell Design Engineer with a focus on radiation-hardened solutions. This is your opportunity to shape the future of resilient microelectronics, leading the development of next-generation standard cell libraries and pioneering simulation tools that predict circuit reliability in extreme environments.

What You'll Do

• Contribute to execution and development of Radiation Hardened LEAP Standard Cell Libraries across multiple foundry technology nodes.
• Generate, characterize and validate new standard cells , electrical circuits and IP, including or containing combinatorial logic , sequential logic, and utility, timing and power management cells .
• Leverage in-house software tools used for calculating and analyzing radiation-induced error rates and circuit reliability.
• E xecute simulations and advanced library characterization to ensure cell resilience and optimize performance (PPA) in harsh environments.
• Directly engage and collaborate with customers , address customer issues and provide design support.
• Interface with external foundry partners on test chip execution efforts on Multi Product Wafer (MPW) runs .
• Champion a culture of technical excellence, continuous learning, and rigorous scientific inquiry.

What You Bring

• Education/Experience:
  • Master's degree with 2 + years of direct industry experience
  • OR Bachelor's degree with 4 + years of direct industry experience
• U.S. Citizenship is required due to the nature of defense-related projects.
• Deep foundational knowledge of semiconductor design methodologies and principles .
• Hands-on experience with standard cell design , circuit design, layout and library characterization , with demonstrated delivery of de sign elements in past projects .
• Expertise in standard cell design flows , including DRC/LVS, timing analysis, and power integrity.
• Extensive experience with semiconductor simulation tools , particularly for library characterization (SPICE/Fast-Spice).
• Proven ability to execute highly technical projects and drive results in a complex engineering environment.

⭐ Bonus Points For

• Direct experience in Radiation Hardened (Rad-Hard) design methodologies, especially in mitigating Single Event Effects (SEE) and Single Event Upsets (SEU) .
• Proficiency in C++ coding and related scripting languages (e.g., Python, TCL) for tool development or advanced simulation/analysis automation.
• Experience working with commercial foundry technology nodes (e.g., FinFET , GAA, SOI, planar).
• Strong desire and demonstrated capacity to quickly learn new physics , methodologies, and technology platforms.