Senior Manager of Semiconductor Technologies

⚙️ Shape the Future of Microelectronics at JRC !

Do you have a passion for cutting-edge technology and driving the future of microelectronics? If so, we want to connect with you! We're on the lookout for a dynamic Senior Manager of Semiconductor Technologies (Radiation-Hardened Focus) to join our team, reporting directly to the Vice President of Semiconductor Technologies. In this high-impact role, you'll lead our Radiation-Hardened Semiconductor Technology Division -a fast-moving, strategic pillar of our innovation portfolio.

As a key technical leader, you'll guide the development of our next-generation radiation-hardened standard cell library and spearhead the advancement of proprietary simulation software that predicts reliability and error rates from radiation effects. This role demands a unique blend of deep device physics expertise , hands-on design and simulation skills, and a strategic mindset to drive innovation from foundry-level processes to circuit-level performance.

What You'll Do

• Mentor, manage, and grow a small, high-performing team of device physicists, circuit designers, and software engineers.
• Contribute to d efin ing the technical roadmap and strategy for the development of Radiation Hardened LEAP Standard Cell Libraries across multiple foundry technology nodes.
• Serve as the technical authority on Semiconductor Device Physics for radiation effects, including Total Ionizing Dose (TID), Single Event Effects (SEE), and Single Event Upsets (SEU).
• Direct the development, maintenance, and enhancement of in-house software tools used for calculating and analyzing radiation-induced error rates and circuit reliability.
• I nterface and collaborate directly with customers , and o versee project execution, timelines, resource allocation, technical quality control , and proactively address customer issues across execution and development efforts.
• Oversee and execute simulations and advanced library characterization efforts to ensure cell resilience and optimize performance (PPA) in harsh environments. Drive continuous improvement in simulation accuracy, speed, and automation for library characterization flows.
• Manage the relationship with external foundry partners to influence test chip execution efforts on Multi Product Wafer (MPW) runs .
• Champion a culture of technical excellence, continuous learning, and rigorous scientific inquiry.

What You Bring

• Education
  • A Ph.D. in Electrical Engineering, Applied Physics, or a related field with 2+ years of direct industry experience
  • OR a master's degree with 5+ years of direct industry experience
  • OR a b achelor's degree with 7+ years of direct industry experience.
• U.S. Citizenship is required due to the nature of defense-related projects.
• Deep foundational knowledge of semiconductor device physics and solid-state materials.
• Hands-on experience with CMOS layout and design principles.
• Extensive experience with semiconductor simulation tools , particularly for TCAD and/or library characterization (SPICE/Fast-Spice).
• Demonstrated experience working with commercial foundry technology nodes (e.g., FinFET , GAA, SOI, planar).
• Proven ability to lead technical projects and drive results in a complex engineering environment.

⭐ Bonus Points For...

• Direct experience in Radiation Hardened (Rad-Hard) design methodologies, especially in mitigating Single Event Effects (SEE) and Single Event Upsets (SEU) .
• Direct experience in standard cell design , circuit design, layout and library characterization.
• Proficiency in C++ coding and related scripting languages (e.g., Python, TCL) for tool development or advanced simulation/analysis automation.
• 1+ years of e xperience leading a small team of engineers or serving as a technical team lead .
• Strong desire and demonstrated capacity to quickly learn new physics , methodologies, and technology platforms.
• Familiarity with standard cell design flows, including DRC/LVS, timing analysis, and power integrity.