ASIC Test Design Engineer

We’re seeking a DFT (Design for Test) Engineer to join a diverse and highly skilled ASIC design team.

Responsibilities:
• Design and implement Design for Testability (DFT) strategies for ASIC designs, applying a thorough understanding of digital design concepts.
• Follow and adhere to the established ASIC development processes and best practices.
• Write and review RTL code using VHDL, Verilog, or SystemVerilog, with strong proficiency in DFT methodologies.
• Work effectively in a team environment, collaborating with cross-functional teams to achieve project goals.

Basic Qualifications
• Bachelor’s degree in Electrical or Computer Engineering with 8+ years of experience, or a Master’s degree with 6+ years of experience
• U.S. Citizenship required
• Proven experience with the full product lifecycle of ASIC design
• Hands-on experience with Cadence and/or Mentor test insertion and ATPG tools
• Knowledge of hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1, and IEEE-1149.6 (AC JTAG)
• Experience implementing memory BIST and logic BIST
• Skilled in generating test patterns and analyzing/debugging test failures
• Experience collaborating with test engineers to deploy ATPG vectors on tester hardware
• Proficiency in HDL (VHDL, Verilog, or SystemVerilog) and scripting languages such as Tcl, Python, or Perl
• Strong communication and presentation skills, with a high level of technical problem-solving ability

Preferred Qualifications:

• Master's Degree in Electrical or Computer Engineering
• Expertise of using Cadence Modus DFT tools
• Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus