Director of Packaging Engineering - CoWoS

Piper Companies is seeking a Director of Packaging Engineering - CoWoS to join our dynamic team onsite 5 days per week in Saratoga, CA. The Ideal Director of Packaging Engineering - CoWoS will spearhead the development and refinement of Chip-on-Wafer-on-Substrate packaging technology for high-performance AI and data center applications.

Responsibilities for the Director of Packaging Engineering - CoWoS

• Lead the advancement of CoWoS packaging technology to enhance chip performance, power, and reliability.
• Develop and refine CoWoS packaging processes to ensure superior thermal, mechanical, and electrical performance.
• Work closely with design, test, and manufacturing teams to ensure seamless chip-package integration.
• Implement strategies to enhance yield and address failure modes across packaging flows.
• Oversee the transition from prototyping to high-volume manufacturing, ensuring smooth ramp-up.
• Collaborate with leading foundries and OSAT partners (TSMC, ASE, Amkor, SPIL, etc) on process qualification and production ramp-up.
• Lead and collaborate with various teams to ensure the seamless integration of advanced multi-die packages.

Qualifications for the Director of Packaging Engineering - CoWoS:

• 15+ years of hands-on experience in advanced semiconductor packaging and interconnect processes.
• Must be eligible to work in the United States and obtain and maintain an Active U.S. Government Secret Clearance.
• Expertise in CoWoS / FOCoS, or FOWLP.
• Proficient in EMIB, InFO, and advanced 2.5D/3D integration technologies
• Strong understanding of thermal management, reliability testing, and signal/power integrity challenges.
• Proven experience working with TSMC and leading OSATs.
• Bachelor's or Master's degree in Electrical Engineering, Materials Science, Mechanical Engineering, or related field.

Compensation/Benefits for the Director of Packaging Engineering - CoWoS:

• Salary Range: $225,000 - $300,000 annually
• Comprehensive Benefits: Medical, Dental, Vision, 401K, PTO, Sick Leave if required by law, and Holidays.

This job opens for applications on 4/30/2025. Applications for this job will be accepted for at least 30 days from the posting date.

Keywords: Semiconductor Packaging, CoWoS, FOCoS, FOWLP, EMIB, InFO, 2.5D/3D Integration, AI Infrastructure, Data Center Applications, Thermal Management, Reliability Testing, Signal Integrity, Power Integrity, TSMC, OSAT Partners, Chip-on-Wafer-on-Substrate, Packaging Engineering, Director of Packaging Engineering

#LI-BR1

#LI-ON-SITE