ICONMA

Exciting opportunities in the Los Angeles, CA area. Looking for Systems Engineers to support FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. You will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families. This work is onsite 5 days per week.

Exciting opportunities in the Los Angeles, CA area. Looking for Systems Engineers to support FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. You will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families. This work is onsite 5 days per week.

Exciting opportunities in the Los Angeles, CA area. Looking for Systems Engineers to support FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. You will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families. This work is onsite 5 days per week.

Exciting opportunities in the Los Angeles, CA area. Looking for Systems Engineers to support FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. You will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families. This work is onsite 5 days per week.

Exciting opportunities in the Los Angeles, CA area. Looking for Systems Engineers to support FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. You will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families. This work is onsite 5 days per week.